Publisher:Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2014
Citation:NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance, Pasadena, California, September 1, 2014
Abstract:
Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring the non-hermetic ceramic flip chip packages into the QML system, it was suggested that class-Y be set up as a new category. A JEDEC G12 task group has developed screening and qualification requirements for Class-Y products through its efforts from 2010 through 2014. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator. The study focused on the reliability issues related to non-hermeticity, fine feature sizes, and high power characteristics of the class-Y type packages. This document summarizes the results of the collaborational study between JPL and Aeroflex.
