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Reliability considerations of ULP scaled CMOS in spacecraft systems.

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dc.contributor.author White, Mark
dc.contributor.author MacNeal, Kristen
dc.contributor.author Cooper, Mark
dc.date.accessioned 2013-05-29T15:25:40Z
dc.date.available 2013-05-29T15:25:40Z
dc.date.issued 2013-01-28
dc.identifier.citation IEEE Reliability and Maintainability Symposium (RAMS), Orlando, Florida, January 28-30, 2012. en_US
dc.identifier.clearanceno 12-5444
dc.identifier.uri http://hdl.handle.net/2014/43182
dc.description.abstract NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2012. en_US
dc.subject reliability en_US
dc.subject ultra low power en_US
dc.subject scaled CMOS en_US
dc.subject spacecraft systems en_US
dc.title Reliability considerations of ULP scaled CMOS in spacecraft systems. en_US
dc.type Preprint en_US
dc.subject.NASATaxonomy Electronics and Electrical Engineering en_US


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