The design of a fault-tolerant, real-time, multi-core computer system

Gostelow, Kim P.

dc.contributor.author	Gostelow, Kim P.
dc.date.accessioned	2012-04-03T20:42:29Z
dc.date.available	2012-04-03T20:42:29Z
dc.date.issued	2011-03-05
dc.identifier.citation	Aerospace Conference, 2011 IEEE , Big Sky, Montana, March 5-12, 2011, DOI: 10.1109/AERO.2011.5747449	en_US
dc.identifier.clearanceno	11-0964
dc.identifier.uri	http://hdl.handle.net/2014/42027
dc.description.abstract	The goal is a fault-tolerant, self-aware, lowpower, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. A second goal is that the system is not difficult to program. The proposed machine decides how to achieve concurrency, in real-time, rather than programmers who now spend considerable effort carefully orchestrating every data item’s location and movement. Closely related, fault-tolerant and power-aware re-organizing behavior is automatic. The driving features of the system are: simple hardware that is modular in the extreme, with no shared memory, and software with significant run-time reorganizing capability.	en_US
dc.description.sponsorship	NASA/JPL	en_US
dc.language.iso	en_US	en_US
dc.publisher	IEEE	en_US
dc.subject	Fault tolerance	en_US
dc.subject	Real time systems	en_US
dc.subject	Computational modeling	en_US
dc.subject	Concurrent computing	en_US
dc.subject	Fault tolerant systems	en_US
dc.subject	Multicore processing	en_US
dc.subject	Programming	en_US
dc.title	The design of a fault-tolerant, real-time, multi-core computer system	en_US
dc.type	Article	en_US
dc.subject.NASATaxonomy	Spacecraft Instrumentation and Astrionics	en_US