JPL Technical Report Server

Mitigating upsets in SRAM based FPGAs from the Xilinix Virtex 2 Family.

Mitigating upsets in SRAM based FPGAs from the Xilinix Virtex 2 Family.

Swift, Gary M.; Yui, Candice C.; Carmichael, Carl; Koga, Rocky; George, Jeffrey S.
URI: http://hdl.handle.net/2014/41193
Date: 2003-09-09
Keywords: FPGA; Single Event Effect (SEE) testing; Xilinx
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2003
Citation: 6th annual Military and Aerospace Programmable Logic Device (MALPD) International Conference, Washington, D.C., September 9-11, 2003

Show full item record

Items in TRS are protected by copyright, but are furnished with U.S. government purpose use rights.

Files in this item

Thumbnail
Name: 03-2304.pdf
Size: 6.859Mb
Format: PDF
View/Open

This item appears in the following Collection(s)

Search


Browse

My Account