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Mitigating upsets in SRAM based FPGAs from the Xilinix Virtex 2 Family.
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Mitigating upsets in SRAM based FPGAs from the Xilinix Virtex 2 Family.
Swift, Gary M.
;
Yui, Candice C.
;
Carmichael, Carl
;
Koga, Rocky
;
George, Jeffrey S.
URI:
http://hdl.handle.net/2014/41193
Date:
2003-09-09
Keywords:
FPGA; Single Event Effect (SEE) testing; Xilinx
Publisher:
Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2003
Citation:
6th annual Military and Aerospace Programmable Logic Device (MALPD) International Conference, Washington, D.C., September 9-11, 2003
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JPL TRS 1992+
JPL TRS 1992+
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