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Testing and qualifying linear integrated circuits for radiation degradation in space

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dc.contributor.author Johnston, Allan H.
dc.contributor.author Rax, Bernard G.
dc.date.accessioned 2009-03-19T17:42:39Z
dc.date.available 2009-03-19T17:42:39Z
dc.date.issued 2006-08-04
dc.identifier.citation 8th European Conference on Radiation and Its Effects on Components and Systems, 2005. RADECS 2005, Cap d'Adge, France, 19-23 Sept. 2005 Page(s):B2-1 - B2-8 en_US
dc.identifier.clearanceno 05-2311
dc.identifier.uri http://hdl.handle.net/2014/41136
dc.description.abstract This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher IEEE en_US
dc.subject analogue integrated circuits en_US
dc.subject integrated circuit design en_US
dc.subject integrated circuit testing en_US
dc.subject radiation effects en_US
dc.subject transistors en_US
dc.title Testing and qualifying linear integrated circuits for radiation degradation in space en_US
dc.type Article en_US


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