JPL Technical Report Server

VLSI design of turbo decoder for integrated communication system on a chip applications

Show simple item record

dc.contributor.author Fang, Wai-Chi
dc.contributor.author Sethuram, Ashwin
dc.contributor.author Belevi, Kemal
dc.date.accessioned 2006-03-28T17:18:51Z
dc.date.available 2006-03-28T17:18:51Z
dc.date.issued 2003-05-23
dc.identifier.citation IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 23, 2003. en
dc.identifier.clearanceno 03-1174
dc.identifier.uri http://hdl.handle.net/2014/38961
dc.description.abstract A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as satellite communications, wireless LAN, digital TV, cable modem, Digital Video Broadcast (DVB), and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watts. en
dc.description.sponsorship NASA/JPL en
dc.format.extent 352743 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2003. en
dc.subject Very Large-Scale Integration (VLSI) Design en
dc.subject turbo decoder en
dc.subject system on a chip en
dc.title VLSI design of turbo decoder for integrated communication system on a chip applications en
dc.type Preprint en


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account