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IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA

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dc.contributor.author Wang, Mandy W.
dc.contributor.author Bolotin, Gary S.
dc.date.accessioned 2006-02-07T23:21:33Z
dc.date.available 2006-02-07T23:21:33Z
dc.date.issued 2004-09-08
dc.identifier.citation MAPLD International Conference, Washington, SC, September 8-10, 2004. en
dc.identifier.clearanceno 04-0990
dc.identifier.uri http://hdl.handle.net/2014/38418
dc.description.abstract Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance. en
dc.description.sponsorship NASA/JPL en
dc.format.extent 1178672 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004 en
dc.subject PowerPC 405 en
dc.subject single event upset (SEU) en
dc.title IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA en
dc.type Preprint en


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