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Onboard FPGA-based SAR processing for future spaceborne systems

Show simple item record Le, Charles Chan, Samuel Cheng, Frank Fang, Winston Fischman, Mark Hensley, Scott Johnson, Robert Jourdan, Michael Marina, Miguel Parham, Bruce Rogez, Francois Rosen, Paul Shah, Biren Taft, Stephanie 2005-11-07T23:20:49Z 2005-11-07T23:20:49Z 2004-04
dc.identifier.citation IEEE 2004 Radar Conference, Philadelphia, PA, April 26, 2004 en
dc.identifier.clearanceno 04-0450
dc.description.abstract We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation. en
dc.description.sponsorship NASA en
dc.format.extent 641917 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004. en
dc.subject SAR processing en
dc.subject algorithm en
dc.subject doppler en
dc.subject spaceborne systems en
dc.title Onboard FPGA-based SAR processing for future spaceborne systems en
dc.type Preprint en

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