JPL Technical Report Server

Onboard FPGA-based SAR processing for future spaceborne systems

Show simple item record

dc.contributor.author Le, Charles
dc.contributor.author Chan, Samuel
dc.contributor.author Cheng, Frank
dc.contributor.author Fang, Winston
dc.contributor.author Fischman, Mark
dc.contributor.author Hensley, Scott
dc.contributor.author Johnson, Robert
dc.contributor.author Jourdan, Michael
dc.contributor.author Marina, Miguel
dc.contributor.author Parham, Bruce
dc.contributor.author Rogez, Francois
dc.contributor.author Rosen, Paul
dc.contributor.author Shah, Biren
dc.contributor.author Taft, Stephanie
dc.date.accessioned 2005-11-07T23:20:49Z
dc.date.available 2005-11-07T23:20:49Z
dc.date.issued 2004-04
dc.identifier.citation IEEE 2004 Radar Conference, Philadelphia, PA, April 26, 2004 en
dc.identifier.clearanceno 04-0450
dc.identifier.uri http://hdl.handle.net/2014/37880
dc.description.abstract We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation. en
dc.description.sponsorship NASA en
dc.format.extent 641917 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004. en
dc.subject SAR processing en
dc.subject algorithm en
dc.subject doppler en
dc.subject spaceborne systems en
dc.title Onboard FPGA-based SAR processing for future spaceborne systems en
dc.type Preprint en


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account