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Power Optimization in Logic Isomers

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dc.contributor.author Panwar, R. en_US
dc.contributor.author Rennels, D. en_US
dc.contributor.author Alkalaj, L. en_US
dc.date.accessioned 2004-10-06T03:50:33Z
dc.date.available 2004-10-06T03:50:33Z
dc.date.issued 1993-11 en_US
dc.identifier.citation Albuquerque, New Mexico, USA en_US
dc.identifier.clearanceno 93-1160 en_US
dc.identifier.uri http://hdl.handle.net/2014/35501
dc.format.extent 129646 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other non-isomorphic graphs transistors VLSI en_US
dc.title Power Optimization in Logic Isomers en_US


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