JPL Technical Report Server

Update on JPL-led CSP/SIP activities (chip scale package/systems-in-a-package)

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dc.contributor.author Ghaffarian, R. en_US
dc.date.accessioned 2004-09-22T23:38:19Z
dc.date.available 2004-09-22T23:38:19Z
dc.date.issued 2001-05-15 en_US
dc.identifier.citation 2nd Annual NEPP Program en_US
dc.identifier.citation Pasadena, CA, USA en_US
dc.identifier.clearanceno 01-1036 en_US
dc.identifier.uri http://hdl.handle.net/2014/12765
dc.format.extent 43778 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other chipscale package solder joint reliability area array package en_US
dc.title Update on JPL-led CSP/SIP activities (chip scale package/systems-in-a-package) en_US


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