JPL Technical Report Server

CMOS digital imager design from a system-on-a-chip perspective

CMOS digital imager design from a system-on-a-chip perspective

Pain, B.; Hancock, B.; Cunningham, T.; Yang, G.; Seshadri, S.; Heynssens, J.; Wrigley, C.
URI: http://hdl.handle.net/2014/10984
Date: 2000-01-04
Citation: 16th IEEE VLSI Design Conference 2003
New Delhi, India

Abstract:

In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip.

Show full item record

Items in TRS are protected by copyright, but are furnished with U.S. government purpose use rights.

Files in this item

Thumbnail
Name: 02-2884.pdf
Size: 2.269Mb
Format: PDF
View/Open

This item appears in the following Collection(s)

Search


Browse

My Account