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CMOS digital imager design from a system-on-a-chip perspective
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CMOS digital imager design from a system-on-a-chip perspective
Pain, B.
;
Hancock, B.
;
Cunningham, T.
;
Yang, G.
;
Seshadri, S.
;
Heynssens, J.
;
Wrigley, C.
URI:
http://hdl.handle.net/2014/10984
Date:
2000-01-04
Citation:
16th IEEE VLSI Design Conference 2003
New Delhi, India
Abstract:
In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip.
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JPL TRS 1992+
JPL TRS 1992+
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