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Validation of an SEU simulation technique for a complex processor: PowerPC7400

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dc.contributor.author Swift, G.M. en_US
dc.contributor.author Rezgui, S. en_US
dc.contributor.author Velazco, R. en_US
dc.date.accessioned 2004-09-17T06:48:23Z
dc.date.available 2004-09-17T06:48:23Z
dc.date.issued 2002-07-15 en_US
dc.identifier.citation NSREC 2002 en_US
dc.identifier.citation Phoenix, AZ, USA en_US
dc.identifier.clearanceno 02-1693 en_US
dc.identifier.uri http://hdl.handle.net/2014/9461
dc.description.abstract Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects. en_US
dc.format.extent 3378309 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other Radiation single event upset fault injection microprocessors en_US
dc.title Validation of an SEU simulation technique for a complex processor: PowerPC7400 en_US


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