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Maximizing Verification Quality & Resources with Formal and UVM

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dc.contributor.author Lim, Chester N
dc.date.accessioned 2021-11-18T17:45:14Z
dc.date.available 2021-11-18T17:45:14Z
dc.date.issued 2020-07-19
dc.identifier.citation DAC - Design Automation Conference 2020, San Francisco, California, July 19-23, 2020
dc.identifier.clearanceno CL#20-0460
dc.identifier.uri http://hdl.handle.net/2014/52416
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US
dc.publisher Pasadena, CA: Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2020
dc.title Maximizing Verification Quality & Resources with Formal and UVM
dc.type Presentation


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