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An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

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dc.contributor.author Hunter, Don J
dc.contributor.author Bolotin, Gary
dc.contributor.author Lias, Malcolm
dc.contributor.author Cheng, Ben
dc.date.accessioned 2021-10-12T17:51:06Z
dc.date.available 2021-10-12T17:51:06Z
dc.date.issued 2020-03-02
dc.identifier.citation 16th International Conference and Exhibition on Device Packaging, Fountain Hills, Arizona USA, March 2-5, 2020
dc.identifier.clearanceno CL#20-1064
dc.identifier.uri http://hdl.handle.net/2014/52248
dc.description.abstract This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.
dc.description.sponsorship NASA/JPL en_US
dc.description.sponsorship NASA/JPL
dc.language.iso en_US
dc.publisher Pasadena, CA: Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2020
dc.title An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics
dc.type Preprint


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