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Guideline for Single-Event Effect (SEE) testing of System on a Chip (SOC) devices

Show simple item record Guertin, Steven M. 2019-04-02T15:59:11Z 2019-04-02T15:59:11Z 2018-02-01
dc.identifier.citation Jet Propulsion Laborary, Pasadena, CA, February 1, 2018 en_US
dc.description.abstract This document develops and describes radiation testing of advanced microprocessors implemented as system on a chip (SOC). It is intended to be comprehensive, though some portions are referred to existing test standards for microelectronics. The document helps readers determine the type of testing appropriate to their device. It reviews device preparation for test, preparation of test software, and development of test methods including custom software and vendor-provided hardware and software. The steps involving taking the SEE data an applying it to develop space rates are roughly covered, utilizing outside sources. Specific examples are provided for the Aeroflex UT699, Boeing Maestro ITC, and Freescale P2020 and P5020 devices. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA: Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2018 en_US
dc.relation.ispartofseries ;JPL Pub 18-2
dc.subject SEE Test Methods en_US
dc.subject rate calculation en_US
dc.subject device preparation en_US
dc.title Guideline for Single-Event Effect (SEE) testing of System on a Chip (SOC) devices en_US
dc.type Technical Report en_US
dc.subject.NASATaxonomy 60 Computer Operations and Hardware en_US

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