Publisher:Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2009
Citation:2009 IEEE Radar Conference, Pasadena, California, May 4-8, 2009
Abstract:
An approach for algorithm specifications and development is described for SMAP’s radar onboard processor with multi-stage demodulation and decimation bandpass digital filter. Point target simulation is used to verify and validate the filter design with the usual radar performance parameters. Preliminary FPGA implementation is also discussed.
