JPL Technical Report Server

Optimized FPGA implementation of multi-rate FIR filters through thread decomposition

Show simple item record

dc.contributor.author Zheng, Jason
dc.contributor.author Nguyen, Kayla
dc.contributor.author He, Yutao
dc.date.accessioned 2015-03-26T22:56:06Z
dc.date.available 2015-03-26T22:56:06Z
dc.date.issued 2010-03-06
dc.identifier.citation 2010 IEEE Aerospace Conference, Big Sky, Montana, March 6-13, 2010 en_US
dc.identifier.clearanceno 10-0832
dc.identifier.uri http://hdl.handle.net/2014/45052
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2010 en_US
dc.subject DSP en_US
dc.title Optimized FPGA implementation of multi-rate FIR filters through thread decomposition en_US
dc.type Presentation en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account