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A 2x2 w-band reference time-shifted phase-lock transmitter array in 65nm CMOS technology

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dc.contributor.author Tang, Adrian
dc.contributor.author Virbila, Gabriel
dc.contributor.author Hsiao, Frank
dc.contributor.author Wu, Hao
dc.contributor.author Murphy, David
dc.contributor.author Mehdi, Imran
dc.contributor.author Siegel, P. H.
dc.contributor.author Chang, M-C. Frank
dc.date.accessioned 2013-12-17T21:45:31Z
dc.date.available 2013-12-17T21:45:31Z
dc.date.issued 2013-06-20
dc.identifier.citation International Microwave Symposium (IMS), Seattle, Washington, June 2-7, 2013 en_US
dc.identifier.clearanceno 13-0987
dc.identifier.uri http://hdl.handle.net/2014/44106
dc.description.abstract This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2013 en_US
dc.subject PLL Reference en_US
dc.subject time-shifting en_US
dc.subject W-band en_US
dc.subject phased array transmitter en_US
dc.title A 2x2 w-band reference time-shifted phase-lock transmitter array in 65nm CMOS technology en_US
dc.type Preprint en_US


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