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Challenges of developing qualification methods for DDR class devices – Part 2

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dc.contributor.author Guertin, Steven M.
dc.date.accessioned 2013-10-17T21:15:39Z
dc.date.available 2013-10-17T21:15:39Z
dc.date.issued 2011-06-29
dc.identifier.citation NEPP Electronic Technology Workshop, Greenbelt, Maryland, June 28-30, 2011 en_US
dc.identifier.clearanceno 11-2509
dc.identifier.uri http://hdl.handle.net/2014/43906
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2011. en_US
dc.subject reliability testing en_US
dc.subject cell retention en_US
dc.subject Double Data Rate 2 (DDR2) en_US
dc.subject DDR3 en_US
dc.title Challenges of developing qualification methods for DDR class devices – Part 2 en_US
dc.type Presentation en_US


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