JPL Technical Report Server

Physics of failure analysis of Xilinx Flip chip CCGA packages.

Show simple item record

dc.contributor.author Suh, Jong-ook
dc.contributor.author Agarwal, Shri
dc.contributor.author Dillon, Peter
dc.contributor.author Sheldon, Doug
dc.date.accessioned 2012-11-07T22:30:15Z
dc.date.available 2012-11-07T22:30:15Z
dc.date.issued 2012-06-11
dc.identifier.citation 3rd Annual NEPP Electronic Technology Workshop (ETW), Greenbelt, Maryland, June 11-13, 2012. en_US
dc.identifier.clearanceno 12-2364
dc.identifier.uri http://hdl.handle.net/2014/42399
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2012. en_US
dc.subject non‐hermetic flip chip en_US
dc.subject reliability testing en_US
dc.subject failure analysis en_US
dc.title Physics of failure analysis of Xilinx Flip chip CCGA packages. en_US
dc.type Presentation en_US
dc.subject.NASATaxonomy Quality Assurance and Reliability en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account