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Single event test methodologies and system error rate analysis for triple modular redundant field programmable gate arrays.

Single event test methodologies and system error rate analysis for triple modular redundant field programmable gate arrays.

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael
URI: http://hdl.handle.net/2014/41837
Date: 2010-09-20
Keywords: single event upsets; triple modular redundancy; field programmable fate array; error rate calculations
Publisher: IEEE International
Citation: Nuclear Science, IEEE Transactions on Volume: 58 , Issue: 3 , Part: 2 Publication Year: 2011 , Page(s): 1040 - 1046 Publication Year: 2011 , Page(s): 1040 - 1046

Abstract:

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

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