Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays

Abstract

This work discusses mitigation selection and qualification techniques for Xilinx reconfigurable field programmable gate arrays (FPGAs). The aim of the paper is to provide readers with a better understanding of the engineering/reliability/project cost relationship that occurs when developing a mitigation strategy for static random access memory (SRAM)-based FPGAs.