JPL Technical Report Server

Reliability of low-pitch, high-I/O area array packages

Show simple item record

dc.contributor.author Ghaffarian, Reza
dc.date.accessioned 2009-10-05T14:48:17Z
dc.date.available 2009-10-05T14:48:17Z
dc.date.issued 2009-04
dc.identifier.uri http://hdl.handle.net/2014/41405
dc.description.abstract This report first provides a body of knowledge (BoK) survey for designing, manufacturing, and testing high-input/output (I/O) and low-pitch area array packages. It then presents test data on design, assembly, and environmental evaluation results for various newly available electronics packages assembled onto printed wiring boards (PWBs). Packages included plastic ball grid arrays (PBGAs) with I/Os up to 1156 and 1-mm pitch, high-I/O chip scale packages (CSPs), low-pitch flip chip, microlead frame/quad flat no lead (MLF/QFN), and small resistors to 0201 size. Finally, it summarizes lessons learned from test results for assembly and environmental testing along with optical, scanning electron microscopy (SEM), and x-ray photomicrographs showing damage progress. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2009. en_US
dc.relation.ispartofseries JPL Publication en_US
dc.relation.ispartofseries 09-15 en_US
dc.subject solder joint reliability en_US
dc.subject ball grid array en_US
dc.subject plastic ball grid arrays (PBGAs) en_US
dc.subject thermal cycle en_US
dc.subject chip scale packages (CSPs) en_US
dc.subject microlead frame (MLF) en_US
dc.subject x-ray en_US
dc.subject failure en_US
dc.title Reliability of low-pitch, high-I/O area array packages en_US
dc.type Technical Report en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account