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Testing and qualifying linear integrated circuits for radiation degradation in space

Testing and qualifying linear integrated circuits for radiation degradation in space

Johnston, Allan H.; Rax, Bernard G.
URI: http://hdl.handle.net/2014/41136
Date: 2006-08-04
Keywords: analogue integrated circuits; integrated circuit design; integrated circuit testing; radiation effects; transistors
Publisher: IEEE
Citation: 8th European Conference on Radiation and Its Effects on Components and Systems, 2005. RADECS 2005, Cap d'Adge, France, 19-23 Sept. 2005 Page(s):B2-1 - B2-8

Abstract:

This paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.

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