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Tradeoffs in flight design upset mitigation in state of the art FPGAs : hardened by design vs. design level hardening.

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dc.contributor.author Swift, Gary M.
dc.contributor.author Roosta, Ramin
dc.date.accessioned 2009-01-21T18:02:53Z
dc.date.available 2009-01-21T18:02:53Z
dc.date.issued 2004-09-09
dc.identifier.citation Military and Aerospace Programmable Logic Device (MALPD)International Conference, Washington, D.C., September 8-10, 2004 en_US
dc.identifier.clearanceno 04-2861
dc.identifier.uri http://hdl.handle.net/2014/41057
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004. en_US
dc.subject FPGA en_US
dc.subject radiation effects en_US
dc.subject single event upset en_US
dc.subject single event latchup en_US
dc.title Tradeoffs in flight design upset mitigation in state of the art FPGAs : hardened by design vs. design level hardening. en_US
dc.type Presentation en_US


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