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Tradeoffs in flight design upset mitigation in state of the art FPGAs : hardened by design vs. design level hardening.
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Tradeoffs in flight design upset mitigation in state of the art FPGAs : hardened by design vs. design level hardening.
Swift, Gary M.
;
Roosta, Ramin
URI:
http://hdl.handle.net/2014/41057
Date:
2004-09-09
Keywords:
FPGA; radiation effects; single event upset; single event latchup
Publisher:
Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004.
Citation:
Military and Aerospace Programmable Logic Device (MALPD)International Conference, Washington, D.C., September 8-10, 2004
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JPL TRS 1992+
JPL TRS 1992+
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