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Optimizations of a hardware decoder for Deep-Space optical communications

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dc.contributor.author Cheng, Michael K.
dc.contributor.author Nakashima, Michael A.
dc.contributor.author Moision, Bruce E.
dc.contributor.author Hamkins, Jon
dc.date.accessioned 2008-07-31T22:19:03Z
dc.date.available 2008-07-31T22:19:03Z
dc.date.issued 2007-03-02
dc.identifier.citation IEEE Transactions On Circuits and Systems—I: Regular Papers, Vol. 55, NO. 2, March doi:200810.1109/TCSI.2007.913733 en_US
dc.identifier.clearanceno 07-0723
dc.identifier.uri http://hdl.handle.net/2014/40884
dc.description.abstract The National Aeronautics and Space Administration has developed a capacity approaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation (PPM) and an outer convolutional code [or serially concatenated PPM (SCPPM)] for deep-space optical communications. Decoding of this code uses the turbo principle. However, due to the nonbinary property of SCPPM, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a pipeline-friendly “maxstar top-2” circuit that reduces the max-only approximation penalty, a low-latency cyclic redundancy check circuit for window-based decoders, and a high-speed algorithmic polynomial interleaver that leads to memory savings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kilobits per second from Mars, the SCPPM coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher IEEE en_US
dc.subject Cyclic redundancy check (CRC) en_US
dc.subject field-programmable gate array (FPGA) implementation en_US
dc.subject optical communications en_US
dc.subject quadratic polynomial interleaver en_US
dc.subject turbo decoding en_US
dc.title Optimizations of a hardware decoder for Deep-Space optical communications en_US
dc.type Article en_US


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