JPL Technical Report Server

Catastrophic fault recovery with self-reconfigurable chips

Show simple item record

dc.contributor.author Zheng, Will Hua
dc.contributor.author Marzwell, Neville I.
dc.contributor.author Chau, Savio N.
dc.date.accessioned 2006-10-31T22:25:24Z
dc.date.available 2006-10-31T22:25:24Z
dc.date.issued 2006-10-04
dc.identifier.citation Computational Engineering in Systems Application, Beijing, China, October 4-6, 2006 en
dc.identifier.clearanceno 06-1968
dc.identifier.uri http://hdl.handle.net/2014/39886
dc.description.abstract Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of “Self-Reconfigurable Chips” as a last resort effort to “repair” a faulty critical component. en
dc.description.sponsorship NASA/JPL en
dc.format.extent 286783 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2006. en
dc.subject Reconfiguration en
dc.subject Field Programmable Gate Array (FPGA) en
dc.subject fault recovery en
dc.subject fault tolerance en
dc.subject Self reconfiguration en
dc.title Catastrophic fault recovery with self-reconfigurable chips en
dc.type Preprint en


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account