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Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

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dc.contributor.author Irom, Farokh
dc.contributor.author Farmanesh, Farhad H.
dc.date.accessioned 2006-03-09T18:40:54Z
dc.date.available 2006-03-09T18:40:54Z
dc.date.issued 2004-09-22
dc.identifier.citation IEEE Transactions On Nuclear Science, Vol. 52, No. 5, October 2005; doi: 10.1109/TNS.2005.855816 en
dc.identifier.clearanceno 04-2616
dc.identifier.uri http://hdl.handle.net/2014/38831
dc.description.abstract Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed en
dc.description.sponsorship NASA/JPL en
dc.format.extent 1221545 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher IEEE en
dc.subject microprocessors en
dc.subject single event upset (SEU) en
dc.title Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors en
dc.type Preprint en


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