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An on-board processor for a spaceborne Doppler precipitation radar : requirements and preliminary design

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dc.contributor.author Durden, Stephen L.
dc.contributor.author Fischman, M. A.
dc.contributor.author Tanelli, S.
dc.contributor.author Johnson, R. A.
dc.contributor.author Chu, A.
dc.date.accessioned 2006-02-08T20:24:56Z
dc.date.available 2006-02-08T20:24:56Z
dc.date.issued 2004-06-22
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004
dc.identifier.citation Earth Science Technology Conference, Palo Alto, CA, June 22-24, 2004 en
dc.identifier.clearanceno 04-1339
dc.identifier.uri http://hdl.handle.net/2014/38450
dc.description.abstract Use of Doppler velocity measurement in spaceborne precipitation radar is highly desirable, since it can allow more accurate retrieval of atmospheric latent heating, which depends on both cloud and rain microphysical processes and on dynamical processes, namely, vertical updrafts and downdrafts. However, if the rain within the antenna beam is very non-uniform, biases can result with conventional pulse-pair processing, and more sophisticated processing is required. The solution is a time-frequency approach, which uses the full Doppler spectrum at each point in time. Since precipitation radars normally operate continuously and collect large amounts of data, real-time, on-board processing of data is needed to reduce the data rate. The objective of this work is to develop an on-board data processor for spaceborne Doppler precipitation radar, using field-programmable gate array (FPGA) technology. This paper describes the simulations and analysis that have been completed during the first year of the project. This includes both analytical calculations and bit-true simulations that allow the effects of finite word length to be explored. Tradeoffs have also been considered between speed and space within the chosen FPGA part. The results of these analyses have been used to develop a complete set of requirements for the processor. Initial design work has begun, based on these requirements. The design is being implemented in Verilog, and a description of this early design effort is also be given. en
dc.description.sponsorship NASA/JPL en
dc.format.extent 1227899 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004 en
dc.subject radar en
dc.subject precipitation en
dc.subject Doppler en
dc.subject on-board processing en
dc.subject field programmable gate array en
dc.title An on-board processor for a spaceborne Doppler precipitation radar : requirements and preliminary design en
dc.type Preprint en


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