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Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

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dc.contributor.author Irom, F.
dc.contributor.author Farmanesh, F. H.
dc.contributor.author Swift, G. M.
dc.contributor.author Johnston, A. H.
dc.contributor.author Yoder, G. I.
dc.date.accessioned 2005-11-16T20:31:29Z
dc.date.available 2005-11-16T20:31:29Z
dc.date.issued 2003-07
dc.identifier.citation IEEE Transactions on Nuclear Science, Monterey, CA, July 21-25, 2003 en
dc.identifier.clearanceno 03-1923
dc.identifier.uri http://hdl.handle.net/2014/38157
dc.description.abstract Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed. en
dc.description.sponsorship NASA en
dc.format.extent 3772620 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en
dc.publisher Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2003. en
dc.subject single event upset en
dc.subject microprocessor en
dc.title Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies en
dc.type Preprint en


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