dc.contributor.author |
Akarvardar, K. |
|
dc.contributor.author |
Chen, S. |
|
dc.contributor.author |
Blalock, B. J. |
|
dc.contributor.author |
Cristoloveanu, S. |
|
dc.contributor.author |
Gentil, P. |
|
dc.contributor.author |
Mojarradi, M. |
|
dc.date.accessioned |
2005-10-11T19:55:40Z |
|
dc.date.available |
2005-10-11T19:55:40Z |
|
dc.date.issued |
2005-09 |
|
dc.identifier.citation |
European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, September 12-16, 2005 |
en |
dc.identifier.clearanceno |
05-1186 |
|
dc.identifier.uri |
http://hdl.handle.net/2014/37675 |
|
dc.description.abstract |
A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. |
en |
dc.description.sponsorship |
NASA |
en |
dc.format.extent |
235650 bytes |
|
dc.format.mimetype |
application/pdf |
|
dc.language.iso |
en_US |
en |
dc.publisher |
Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2005. |
en |
dc.subject |
SOI CMOS |
en |
dc.subject |
analog multiplier |
en |
dc.title |
A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs) |
en |
dc.type |
Preprint |
en |