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A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs)

A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs)

Akarvardar, K.; Chen, S.; Blalock, B. J.; Cristoloveanu, S.; Gentil, P.; Mojarradi, M.
URI: http://hdl.handle.net/2014/37675
Date: 2005-09
Keywords: SOI CMOS; analog multiplier
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2005.
Citation: European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, September 12-16, 2005

Abstract:

A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.

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