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Parallel VLSI equalizer architectures for multi-Gbps satellite communications

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dc.contributor.author Ghuman, P. en_US
dc.contributor.author Gray, A. A.
dc.contributor.author Hoy, S. D.
dc.date.accessioned 2004-11-09T21:38:39Z
dc.date.available 2004-11-09T21:38:39Z
dc.date.issued 2001-11-25 en_US
dc.identifier.citation IEEE Globecom 2001 en_US
dc.identifier.citation San Antonio, TX, USA en_US
dc.identifier.clearanceno 01-1873 en_US
dc.identifier.uri http://hdl.handle.net/2014/36851
dc.description.abstract This paper provides an overview of a new very large scale integration (VLSI) architecture for implementing a frequency domain least-mean squares (LMS) complex equalizer. en_US
dc.format.extent 463194 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other pulse position modulation optical communications adaptive threshold receiver ROC en_US
dc.title Parallel VLSI equalizer architectures for multi-Gbps satellite communications en_US


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