Prototyping and FPGA-based MAP synchronizer for very high rate FQPSK

Gray, A.; Kang, E.

dc.contributor.author	Gray, A.	en_US
dc.contributor.author	Kang, E.
dc.date.accessioned	2004-11-09T21:16:58Z
dc.date.available	2004-11-09T21:16:58Z
dc.date.issued	2001-10-22	en_US
dc.identifier.citation	International Telemetry Conference, 2001	en_US
dc.identifier.citation	Las Vegas, NV, USA	en_US
dc.identifier.clearanceno	01-0361	en_US
dc.identifier.uri	http://hdl.handle.net/2014/36731
dc.description.abstract	While fundamental formulations of maximum a posteriori (MAP) estimation for symbol timing [1] have been in exisence for some time, it has generally not seen widespread usage in communications receivers due to its relatively greater complexity in comparison to other designs. However, MAP has been shown to provide significant performance advantages for the acquisition and tracking of digital modulations under low SNR conditions when compared to traditional techniques, such as the data transition tracking loop [2].	en_US
dc.format.extent	78319 bytes
dc.format.mimetype	application/pdf
dc.language.iso	en_US
dc.subject.other	FPGA FQPSK communications receiver high speed synchronizer digital modulation tracking	en_US
dc.title	Prototyping and FPGA-based MAP synchronizer for very high rate FQPSK	en_US