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Embeddable Reconfigurable Neuroprocessors

Show simple item record Daud, Taher en_US Duong, Tuan en_US Harry Langenbacher en_US Tran, Mua en_US Thakoor, Anil en_US 2004-10-06T04:38:02Z 2004-10-06T04:38:02Z 1993-11-14 en_US
dc.identifier.citation St. Louis, MO, USA en_US
dc.identifier.clearanceno 93-1422 en_US
dc.description.abstract Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described. en_US
dc.format.extent 357100 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other Neuroprocessors en_US
dc.title Embeddable Reconfigurable Neuroprocessors en_US

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