JPL Technical Report Server

Embeddable Reconfigurable Neuroprocessors

Show simple item record

dc.contributor.author Daud, Taher en_US
dc.contributor.author Duong, Tuan en_US
dc.contributor.author Harry Langenbacher en_US
dc.contributor.author Tran, Mua en_US
dc.contributor.author Thakoor, Anil en_US
dc.date.accessioned 2004-10-06T04:38:02Z
dc.date.available 2004-10-06T04:38:02Z
dc.date.issued 1993-11-14 en_US
dc.identifier.citation St. Louis, MO, USA en_US
dc.identifier.clearanceno 93-1422 en_US
dc.identifier.uri http://hdl.handle.net/2014/35699
dc.description.abstract Reconfigurable and cascadable building block neural network chips, fabricated using analog VLSI design tools, are interfaced to a PC. The building block chip designs, the cascadability and the hardware-in-the-loop supervised learning aspects of these chips are described. en_US
dc.format.extent 357100 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other Neuroprocessors en_US
dc.title Embeddable Reconfigurable Neuroprocessors en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search


Browse

My Account