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Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

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dc.contributor.author Mendis, Sunetra K. en_US
dc.contributor.author Pain, Bedabrata en_US
dc.contributor.author Nixon, Robert H. en_US
dc.contributor.author Fossum, Eric R. en_US
dc.date.accessioned 2004-10-06T01:32:49Z
dc.date.available 2004-10-06T01:32:49Z
dc.date.issued 1993-02 en_US
dc.identifier.citation SPIE/IS&T: Electronic Imaging en_US
dc.identifier.citation San Jose, CA en_US
dc.identifier.clearanceno 93-0399 en_US
dc.identifier.uri http://hdl.handle.net/2014/34949
dc.description.abstract The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance. en_US
dc.format.extent 288705 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.title Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion en_US


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