Low Power Analog Neurosynapse Chips for a 3-D "Sugarcube" Neuroprocessor

Duong, T.; Kemeny, S.; Tran, M.; Daud, T.; Thakoor, A.

dc.contributor.author	Duong, T.	en_US
dc.contributor.author	Kemeny, S.	en_US
dc.contributor.author	Tran, M.	en_US
dc.contributor.author	Daud, T.	en_US
dc.contributor.author	Thakoor, A.	en_US
dc.date.accessioned	2004-10-05T21:06:11Z
dc.date.available	2004-10-05T21:06:11Z
dc.date.issued	1994-06-26	en_US
dc.identifier.citation	IEEE, Computational Intelligence	en_US
dc.identifier.citation	Honolulu, Hawaii, USA	en_US
dc.identifier.clearanceno	94-0417	en_US
dc.identifier.uri	http://hdl.handle.net/2014/33690
dc.description.abstract	Object discrimination and patttern recognition are computationally intensive and for many defense and commercial applications, speed is of the essence.	en_US
dc.format.extent	89178 bytes
dc.format.mimetype	application/pdf
dc.language.iso	en_US
dc.subject.other	3-D VLSI architecture reconfigurable multilayer perceptron synapse neuron pair	en_US
dc.title	Low Power Analog Neurosynapse Chips for a 3-D "Sugarcube" Neuroprocessor	en_US