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(abstract) A High Throughput 3-D Inner Product Processor

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dc.contributor.author Daud, Tuan en_US
dc.date.accessioned 2004-10-01T05:20:21Z
dc.date.available 2004-10-01T05:20:21Z
dc.date.issued 1996-10-07 en_US
dc.identifier.citation Minneapolis, MN en_US
dc.identifier.clearanceno 96-1451 en_US
dc.identifier.uri http://hdl.handle.net/2014/27359
dc.description.abstract A particularily challenging image processing application is the real time scene acquisition and object discrimination. It requires spatio-temporal recognition of point and resolved objects at high speeds with parallel processing algorithms. Neural network paradigms provide fine grain parallism and, when implemented in hardware, offer orders of magnitude speed up. However, neural networks implemented on a VLSI chip are planer architectures capable of efficient processing of linear vector signals rather than 2-D images. Therefore, for processing of images, a 3-D stack of neural-net ICs receiving planar inputs and consuming minimal power are required. Details of the circuits with chip architectures will be described with need to develop ultralow-power electronics. Further, use of the architecture in a system for high-speed processing will be illustrated. en_US
dc.format.extent 261992 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other image processing scene acquisition object discrimination spatio-temporal recognition neural networks VLSI chips analog-digital hybrids 2-D imaging 3-D imaging parallel processing algorithms linear vector signals en_US
dc.title (abstract) A High Throughput 3-D Inner Product Processor en_US


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