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A Systems Approach for Quality and Reliability of Chip Scale Package Assembly

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dc.contributor.author Ghaffarian, R. en_US
dc.date.accessioned 2004-09-25T17:33:42Z
dc.date.available 2004-09-25T17:33:42Z
dc.date.issued 1999-03-06 en_US
dc.identifier.citation MTG: 1999 IEEE Aerospace Conference en_US
dc.identifier.citation Aspen, CO, U.S.A. en_US
dc.identifier.clearanceno 98-1780 en_US
dc.identifier.uri http://hdl.handle.net/2014/20718
dc.description.abstract This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COSTS) chip scale package (CSP) assemblies. en_US
dc.format.extent 610579 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other CSP Chip Scale Package Solder Joint Reliability Thermal cycling Ball Grid Array en_US
dc.title A Systems Approach for Quality and Reliability of Chip Scale Package Assembly en_US


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