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Winner/Loser-Take-All Circuits on SOI Technology for Neural Network Classification

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dc.contributor.author Duong, T. en_US
dc.contributor.author Saunders, C. en_US
dc.contributor.author Ngo, T. en_US
dc.contributor.author Daud, T. en_US
dc.date.accessioned 2004-09-24T20:22:26Z
dc.date.available 2004-09-24T20:22:26Z
dc.date.issued 1998-04-13 en_US
dc.identifier.citation Applications and Science of Computational Intelligence en_US
dc.identifier.citation Orlando, FL, U.S.A. en_US
dc.identifier.clearanceno 98-0383 en_US
dc.identifier.uri http://hdl.handle.net/2014/19138
dc.description.abstract High connectivity of artificial neural network chip-embodiments combined with currently emerging 3-dimensionally stacked multichip modules for real-time applications of target classification require a scrutiny for low power technology insertion. en_US
dc.format.extent 770507 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other neural network Winner/Loser-Take-All (W/LTA) Circuts Silicon-On-Insulator (SOI) technology en_US
dc.title Winner/Loser-Take-All Circuits on SOI Technology for Neural Network Classification en_US


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