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Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits

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dc.contributor.author Stoica, A. en_US
dc.contributor.author Keymeulen, D. en_US
dc.contributor.author Tawel, R. en_US
dc.contributor.author Salazar-Lazaro, C. en_US
dc.contributor.author Li, W. en_US
dc.date.accessioned 2004-09-24T16:21:08Z
dc.date.available 2004-09-24T16:21:08Z
dc.date.issued 1999-07-19 en_US
dc.identifier.citation First NASA/DoD Workshop on Evolvable Hardware en_US
dc.identifier.citation Pasadena, California, USA en_US
dc.identifier.clearanceno 99-1190 en_US
dc.identifier.uri http://hdl.handle.net/2014/17747
dc.description.abstract The paper describes the architectual details of a fine-grained Programmable Transistor Array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. en_US
dc.format.extent 1003317 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other evolvable hardware reconfigurable hardware genetic algorithms adaptive computing en_US
dc.title Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits en_US


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