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ELIPS: Toward a Sensor Fusion Processor on a Chip

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dc.contributor.author Daud, T. en_US
dc.contributor.author Stoica, A. en_US
dc.contributor.author Tyson, T. en_US
dc.contributor.author Li, W. en_US
dc.contributor.author Fabunmi, J. en_US
dc.date.accessioned 2004-09-23T22:56:06Z
dc.date.available 2004-09-23T22:56:06Z
dc.date.issued 1999-04-05 en_US
dc.identifier.citation SPIE, AeroSence 1999 en_US
dc.identifier.citation Orlando, Florida, USA en_US
dc.identifier.clearanceno 99-0167 en_US
dc.identifier.uri http://hdl.handle.net/2014/16766
dc.description.abstract The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. en_US
dc.format.extent 1151256 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other sensor fusion hardware sensor fusion processor neural networks fuzzy expert system reconfigurable hardware en_US
dc.title ELIPS: Toward a Sensor Fusion Processor on a Chip en_US


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