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Speed challenge: a case for hardware implementation in soft-computing

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dc.contributor.author Daud, T. en_US
dc.contributor.author Stoica, A. en_US
dc.contributor.author Duong, T. en_US
dc.contributor.author Keymeulen, D. en_US
dc.contributor.author Zebulum, R. en_US
dc.contributor.author Thomas, T. en_US
dc.contributor.author Thakoor, A. en_US
dc.date.accessioned 2004-09-23T21:40:09Z
dc.date.available 2004-09-23T21:40:09Z
dc.date.issued 2000-09-12 en_US
dc.identifier.citation 3rd International Conference on Information Technology en_US
dc.identifier.citation Bhubarieswar, India en_US
dc.identifier.clearanceno 00-2021 en_US
dc.identifier.uri http://hdl.handle.net/2014/16115
dc.description.abstract For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities. en_US
dc.format.extent 1334504 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other neural networks fuzzy logic evolvable hardware soft computing parallel processors en_US
dc.title Speed challenge: a case for hardware implementation in soft-computing en_US


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