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Asynchronous FPGA risks

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dc.contributor.author Erickson, K. en_US
dc.date.accessioned 2004-09-23T21:19:58Z
dc.date.available 2004-09-23T21:19:58Z
dc.date.issued 2000-09-26 en_US
dc.identifier.citation Military and Aerospace Applications of Programmable Devices and Technologies en_US
dc.identifier.citation Laurel, Maryland, USA en_US
dc.identifier.clearanceno 00-1808 en_US
dc.identifier.uri http://hdl.handle.net/2014/15983
dc.description.abstract The worst case timing margin of a synchronous design implemented with a field-programmable gate array (FPGA) is easy to perform using available FPGA design tools. However, it may be difficult to impossible to verify that worst case timing requirements are met for complex asynchronous logic design. en_US
dc.format.extent 816194 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other risk FPGA asynchronous en_US
dc.title Asynchronous FPGA risks en_US


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