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Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test

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dc.contributor.author Ghaffarian, R. en_US
dc.date.accessioned 2004-09-23T21:16:25Z
dc.date.available 2004-09-23T21:16:25Z
dc.date.issued 2000-08-15 en_US
dc.identifier.citation Chip scale package review en_US
dc.identifier.clearanceno 00-1740 en_US
dc.identifier.uri http://hdl.handle.net/2014/15937
dc.description.abstract A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. en_US
dc.format.extent 622282 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other Chip Scale Package CSP thermal cycle fatigue solder joint reliability en_US
dc.title Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test en_US


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