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Extreme temperature (-170C to + 125C) electronics for nanorover operation
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| dc.contributor.author | Newell, M. | en_US |
| dc.contributor.author | Buchanan, C. | en_US |
| dc.contributor.author | McCarthy, T. | en_US |
| dc.contributor.author | Cozy, S. | en_US |
| dc.contributor.author | Gregoire, T. | en_US |
| dc.contributor.author | Stern, R. | en_US |
| dc.date.accessioned | 2004-09-23T21:13:42Z | |
| dc.date.available | 2004-09-23T21:13:42Z | |
| dc.date.issued | 2000-08-08 | en_US |
| dc.identifier.citation | 2001 IEEE Aerospace Conference | en_US |
| dc.identifier.citation | Big Sky, Montana, USA | en_US |
| dc.identifier.clearanceno | 00-1690 | en_US |
| dc.identifier.uri | http://hdl.handle.net/2014/15900 | |
| dc.format.extent | 26993 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en_US | |
| dc.subject.other | CMOS extreme temperatures chip on board low power low mass low volume radiation hardened | en_US |
| dc.title | Extreme temperature (-170C to + 125C) electronics for nanorover operation | en_US |
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JPL TRS 1992+
JPL TRS 1992+