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CSP Assembly Reliability and Effects of Underfill and Double-Sided Population
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| dc.contributor.author | Ghaffarian, R. | en_US |
| dc.contributor.author | Kim, N. | en_US |
| dc.date.accessioned | 2004-09-23T17:21:44Z | |
| dc.date.available | 2004-09-23T17:21:44Z | |
| dc.date.issued | 2000-05-21 | en_US |
| dc.identifier.citation | IEEE Electronic Components on Technology Center | en_US |
| dc.identifier.citation | Las Vegas, Nevada, USA | en_US |
| dc.identifier.clearanceno | 00-0117 | en_US |
| dc.identifier.uri | http://hdl.handle.net/2014/13748 | |
| dc.description.abstract | The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. | en_US |
| dc.format.extent | 631907 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | en_US | |
| dc.subject.other | chip scale package CSP solder joint reliability underfill double-sided assembly | en_US |
| dc.title | CSP Assembly Reliability and Effects of Underfill and Double-Sided Population | en_US |
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JPL TRS 1992+
JPL TRS 1992+