JPL Technical Report Server

CMOS sum and difference imager with on-chip charge-leakage compensation

CMOS sum and difference imager with on-chip charge-leakage compensation

Seshadri, S.; Yang, G.; Ortiz, M.; Wrigley, C.; Pain, B.
URI: http://hdl.handle.net/2014/12827
Date: 2001-05-21
Citation: 2001 IEEE Workshop on CCDs and Advanced Image Sensors
Lake Tahoe, Nevada, USA

Abstract:

This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and summ of two successive frames.

Show full item record

Items in TRS are protected by copyright, but are furnished with U.S. government purpose use rights.

Files in this item

Thumbnail
Name: 01-1148.pdf
Size: 324.2Kb
Format: PDF
View/Open

This item appears in the following Collection(s)

Search


Browse

My Account