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CMOS digital imager design from a system-on-a-chip perspective

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dc.contributor.author Pain, B. en_US
dc.contributor.author Hancock, B. en_US
dc.contributor.author Cunningham, T. en_US
dc.contributor.author Yang, G. en_US
dc.contributor.author Seshadri, S. en_US
dc.contributor.author Heynssens, J. en_US
dc.contributor.author Wrigley, C. en_US
dc.date.accessioned 2004-09-17T19:44:14Z
dc.date.available 2004-09-17T19:44:14Z
dc.date.issued 2000-01-04 en_US
dc.identifier.citation 16th IEEE VLSI Design Conference 2003 en_US
dc.identifier.citation New Delhi, India en_US
dc.identifier.clearanceno 02-2884 en_US
dc.identifier.uri http://hdl.handle.net/2014/10984
dc.description.abstract In this paper, we have identified timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. en_US
dc.format.extent 2380198 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject.other CMOS imager noise en_US
dc.title CMOS digital imager design from a system-on-a-chip perspective en_US


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